Essentials Of Computer Organization And Architecture 6th Edition Linda Null, Julia Labur - Solutions

How do memory-memory, register-memory, and load-store architectures differ? How are they the same?
True Or False: Fixed-length instruction format typically results in better performance than variable-length instruction format.
What are the pros and cons of fixed-length and variable-length instructions? Which is currently more popular?
The Population Studies Institute monitors the population of the United States. In 2008, this institute wrote a program to create files of the numbers representing populations of the various states, as well as the total population of the United States. This program, which runs on a Motorola
True Or False: Expanding opcodes make instruction decoding much easier than when it is not used.
How does an architecture based on zero operands ever get any data values from memory?
There are reasons for machine designers to want all instructions to be the same length. Why is this not a good idea on a stack machine?
True Or False: Instruction set orthogonality refers to the characteristic in an instruction set architecture where each instruction has a “backup” instruction that performs the same operation.
Which is likely to be longer (have more instructions): a program written for a zero-address architecture, a program written for a one address architecture, or a program written for a two-address architecture? Why?
True Or False: The effective address of an operand is the value of its actual address in memory.
Convert the following expressions from infix to reverse Polish (postfix) notation. a) (8-6)/2 b) (2+3) × 8/10 c) (5 × (4 + 3) × 2 - 6) x
Why might stack architectures represent arithmetic expressions in reverse Polish notation?
True Or False: Resource conflicts occur in a pipeline when there are multiple instructions that require the same resource.
Convert the following expressions from reverse Polish notation to infix notation. a) 12 8 3 1 +-1 b) 5 2 + 2 x 1 + 2 x c) 357 +21-x 1 ++
Name the seven types of data instructions and explain each.
Convert the following expressions from reverse Polish notation to infix notation a) WXYZ- + X b) UVWXYZ+X+X+ c) X Y Z + VW - X Z++
Explain what it means for an instruction set to be orthogonal.
What is an address mode?
a) Write the following expression in postfix (reverse Polish) notation. Remember the rules of precedence for arithmetic operators b) Write a program to evaluate the above arithmetic statement using a stack- organized computer with zero-address instructions (so only Pop and Push can access memory).
Give examples of immediate, direct, register, indirect, register indirect, and indexed addressing.
a) In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have using the specified format? Justify your answer. b) Assume that a computer architect has already designed 6 two address and 24 zero-address instructions using
How does indexed addressing differ from based addressing?
Why do we need so many different addressing modes?
Suppose a computer has an instruction format with space for an opcode and either three register values or one register value and an address. What are the various instruction formats that could be used for an ADD instruction on this machine?
Given 16-bit instructions, is it possible to use expanding opcodes to allow the following to be encoded assuming we have a total of 32 registers? If so, show the encoding. If not, explain why is it not possible o 60 instructions o 30 instructions with two register operands with one register
Explain the concept behind instruction pipelining.
What is the theoretical speedup for a four-stage pipeline with a 20ns clock cycle if it is processing 100 tasks?
What is the difference between using direct and indirect addressing? Give an example.
Suppose we have the instruction Load 1000. Given that memory and register R1 contain the values belowand assuming that R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below:
What are the pipeline conflicts that can cause a slowdown in the pipeline?
Suppose we have the instruction Load 500. Given that memory and register R1 contain the values below and assuming that R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below:
What are the two types of ILP, and how do they differ?
Explain superscalar, superpipe lining, and VLIW architectures.
List several ways in which the Intel and MIPS ISAs differ. Name several ways in which they are the same.
A nonpipelined system takes 100ns to process a task. The same task can be processed in a five-stage pipeline with a clock cycle of 20ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the theoretical speedup that could be achieved with the pipeline system over a nonpipelined
Explain Java bytecodes.
Give an example of a current stack-based architecture and a current GPR-based architecture. How do they differ?
Write a for loop in ARM assembly language to implement the following pseudocode sum = 0; for (x = 1 to 10); sum + X; sum endfor;
Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes four
Which is faster, SRAM or DRAM?
Suppose a computer using direct-mapped cache has 2 20 bytes of byte-addressable main memory and a cache of 32 blocks, where each cache block contains 16 bytesa) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache; that is, what are the sizes of
What are the advantages of using DRAM for main memory?
Suppose a computer using direct-mapped cache has 2 32 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytesa) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache; that is, what are the sizes
Name three different applications where ROMs are often used.
Suppose a computer using direct-mapped cache has 2 32 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytesa) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache; that is, what are the sizes of
Suppose a computer using fully associative cache has 2 16 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytesa) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache; that is, what are the
Explain the concept of a memory hierarchy. Why did your authors choose to represent it as a pyramid?
Suppose a computer using fully associative cache has 2 24 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytesa) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache; that is, what are the
Explain the concept of locality of reference, and state its importance to memory systems.
Suppose a computer using fully associative cache has 2 24 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache; that is, what are the sizes of the
What are the three forms of locality?
Assume that a system’s memory has 128M bytes. Blocks are 64 bytes in length, and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way set-associative cache mapping scheme and byte addressing. Be sure to include the fields as well as their sizes.
Give two noncomputer examples of the concept of cache.
A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressing is useda) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b) Compute the hit
Which of L1 or L2 cache is faster? Which is smaller? Why is it smaller?
Suppose a byte-addressable computer using set-associative cache has 2 16 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytesa) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the
Cache is accessed by its _______, whereas main memory is accessed by its _______.
Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program.Suppose this computer uses direct-mapped cache. The format of a memory
Suppose a byte-addressable computer using set-associative cache has 2 21 bytes of main memory and a cache of 64 blocks, where each cache block contains 4 bytesa) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the
What are the three fields in a direct-mapped cache address? How are they used to access a word located in cache?
Given a byte-addressable memory with 256 bytes, suppose a memory dump yields the results shown below. The address of each memory cell is determined by its row and column. For example, memory address 0x97 is in the 9th row, 7th column, and contains the hexadecimal value 43. Memory location 0xA3
How does associative memory differ from regular memory? Which is more expensive and why?
Explain how fully associative cache is different from direct mapped cache.
A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into cache.)
Explain how set-associative cache combines the ideas of direct and fully associative cache.
Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing a total of 64KB of data, and blocks of 32 bytes. Show the format of a 24-bit memory address for a) Direct mapped b) Associative c) 4-way set associative
Direct-mapped cache is a special case of set-associative cache where the set size is 1. So fully associative cache is a special case of setassociative cache where the set size is _______.
Suppose a byte-addressable computer using 4-way set-associative cache has 2 16 words of main memory (where each word is 32 bits) and a cache of 32 blocks, where each block is four words. Show the main memory address format for this machine. (Hint: Because this architecture is byte addressable, and
What are the three fields in a set-associative cache address, and how are they used to access a location in cache?
Explain the four cache replacement policies presented in this chapter.
Why is the optimal cache replacement policy important?
What is the worst-case cache behavior that can develop using LRU and FIFO cache replacement policies?
What, exactly, is effective access time (EAT)?
Explain how to derive an effective access time formula.
When does caching behave badly?
What is a dirty block?
Describe the advantages and disadvantages of the two cache write policies.
Explain the difference between a unified cache and a Harvard cache.
What are the advantages of a Harvard cache?
Why would a system contain a victim cache? A trace cache?
Explain the differences among L1, L2, and L3 cache.
Explain the differences between inclusive and exclusive cache.
Name two ways that, as a programmer, you can improve cache performance.
What is the advantage of a nonblocking cache?
Look up a specific vendor’s specifications for memory, and report the memory access time, cache access time, and cache hit rate (and any other data the vendor provides).
What is the difference between a virtual memory address and a physical memory address? Which is larger? Why?
What is the objective of paging?
Discuss the pros and cons of paging.
What is a page fault?
What causes internal fragmentation?
What are the components (fields) of a virtual address?
What is a TLB, and how does it improve EAT?
What are the advantages and disadvantages of virtual memory?
What causes external fragmentation, and how can it be fixed?
State Amdahl’s Law in words.
Calculate the overall speedup of a system that spends 65% of its time on I/O with a disk upgrade that provides for 50% greater throughput.
What is speedup?
Calculate the overall speedup of a system that spends 40% of its time in calculations with a processor upgrade that provides for 100% greater throughput.
Suppose your company has decided that it needs to make certain busy servers 50% faster. Processes in the workload spend 60% of their time using the CPU and 40% on I/O. In order to achieve an overall system speedup of 25%: a. How much faster does the CPU need to be? b. How much faster does the
Name three types of durable storage.

Showing 800 - 900 of 1321

Essentials Of Computer Organization And Architecture 6th Edition Linda Null, Julia Labur - Solutions

Step by Step Answers