8.4-2. To satisfy the steady-state constraints for the system of Problem 8.2-3, the dc gain of the digital controller must be equal 4

(a) Design a phase-lag controller with this dc gain that will result in a \(45^{\circ}\) phase margin.
(b) Estimate the percentage of overshoot in the step response of the compensated system.

(c) Verify the step-response results in part (b) using MATLAB. The step response will show an overshoot in the step response of approximately 24 percent.

Problem 8.2-3

Problem 8.2-2

Transcribed Image Text:

Consider the system of Problem 8.2-2. It is desired that the steady-state error constant for a unit-ramp input, K, of (6-20), be 4, resulting in a steady-state error of 0.25. (a) Repeat Problem 8.2-2(a), (b), (c), and (d) for this system. (b) Use the phase margin om and Fig. 8-2 to estimate the characteristics , M,, and Mp. (c) Verify the value of M, in part (b) using MATLAB. The step response will show that Mp 1.62.