Design an 8:1 multiplexer with the shortest possible delay from the data inputs to the output. You may use any of the gates from Table 2.7 on page 92. Sketch a schematic. Using the gate delays from the table, determine this delay.

Table 2.7 Timing specifications for multiplexer circuit elements Gate tpd (ps) NOT 30 2-input AND 60 3-input AND 80 4-input OR 90 tristate (A to Y) 50 tristate (enable to Y) 35