Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are given in Table 2.8 (and only the gates in that table are available). Design your decoder to have the shortest possible critical path, and indicate what that path is. What are its propagation delay and contamination delay?

Table 2.8 Gate delays for Exercises 2.432.47 (sd) Pd, 15 Gate ted (ps) NOT 10 15 2-input NAND 20 3-input NAND 30 25 2-input NOR 30 25 3-input NOR 45 35 2-input AND 30 25 3-input AND 40 30 2-input OR 40 30 3-input OR 55 45 2-input XOR 60 40