Find the critical path for the 4 ? 4 divider from Figure 5.20 in terms of a 2:1 mux delay (t_MUX), an adder delay (t_FA), and an inverter delay (t_INV). What is the delay of an N ? N divider built in the same way?

A3 A2 A, Ao Bo B, A3 A2 B, B2 B B. A, Ao B2 A B to te AB, AB, A,B, ABo AB, AB, A,B, AB, B3 AB, A,B, A;B, AoB2 to 0- AB, A2B, A;B, AoB3 P, Pe Ps P. Pa P2 Po Pe Ps P4 P3 P2 P Po (a) (b) (c) RDL