Write HDL code for the multicycle MIPS processor. The processor should be compatible with the following top-level module. The mem module is used to hold both instructions and data. Test your processor using the testbench from Section 7.6.3?

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module top(input logic clk, reset, output logic [31:0] writedata, adr. output logic memwrite); logic [31:0] readdata; // instantiate processor and memories mips mips (clk, reset, adr, writedata, memwrite, readdata); mem mem (clk, memwrite, adr, writedata, readdata); endmodule module mem(input logic clk, we, input logic [31:0] a, wd, output logic [31:0] rd); logic [31:0] RAM[63:0]; initial begin $readmemh ( "memfile.dat", RAM); end