Question: Consider a datapath FSM with a five-bit state register state whose next-state function is described by the following VHDL statement: nxt

Consider a datapath FSM with a five-bit state register state whose next-state function is described by the following VHDL statement: 

nxt <= "00001" when rst = ’1’ else (state(3 downto 0) & (state(4) xor state(2))); 

Draw a state diagram for this FSM. Describe in plain English what function this FSM performs.

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