A block diagram and state graph for a divider for unsigned binary numbers is shown subsequently. This divider divides a 16-bit dividend by a 16-bit divisor to give a 16-bit quotient. The divisor can be any number in the range 1 to 2¹⁶- 1. The only case where an overflow can occur is when the divisor is 0. Control signals are defined as follows: Ld1€”load the divisor from the input bus; Ld2€”load the dividend from the input bus and clear ACC; Sh€”left shift ACC and Dividend; Su€”load the subtracter output into ACC and set the lower quotient bit to 1; K = 1 when 15 shifts have been made. Write complete Verilog code for the divider. Use always blocks. 

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Input Quotient Sh Ld2 Su ACC(16) Dividend(16) Counter Control K Ld1 B (borrow) Subtractor Št -IL42 S2 – Ld1 Divisor -/Sh St/Ld1 BK'ISh BK/0 So S3 St'/0 B' KISU B'K'ISu