This problem concerns the design of a divider for unsigned binary numbers that will divide a 16-bit dividend by an 8-bit divisor to give an 8-bit quotient. Assume that the start signal (ST = 1) is 1 for exactly one clock time. If the quotient would require more than 8 bits, the divider should stop immediately and output V = 1 to indicate an overflow. Use a 17-bit dividend register and store the quotient in the lower 8 bits of this register. Use a 4-bit counter to count the number of shifts, together with a subtract-shift controller.
(a) Draw a block diagram of the divider.
(b) Draw a state graph for the subtract-shift controller (three states).
(c) Write a Verilog description of the divider. Use two always blocks, as in Figure 4-40.
(d) Write a test bench for your divider (similar to Figure 4-55).