Question: (a) Draw a logic diagram (use gates, adders, MUXes, D flip-flops, etc.) that shows the result of synthesizing the following Verilog code. A, B, and

(a) Draw a logic diagram (use gates, adders, MUXes, D flip-flops, etc.) that shows the result of synthesizing the following Verilog code. A, B, and C are 3-bit
unsigned vectors.

always @(negedge CLK)

begin

if(C0 == 1)

C <= ~A;

if(Ad == 1)

C <= A + B;

if(Sh == 1)

C <= C >>> 1;

end

(b) Describe in one or two sentences what this circuit does.

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