Question: The following state table is implemented using a ROM and two D flip-flops (falling edge triggered): (a) Draw the block diagram. (b) Write Verilog code

The following state table is implemented using a ROM and two D flip-flops (falling edge triggered):

Q,+Q,* X = 0 X = 1 Q,Q2 X = 0 X = 1 00 01 10 01 10 00 10 00 01 1

(a) Draw the block diagram.
(b) Write Verilog code that describes the system. Assume that the ROM has a delay of 10ns and each flip-flop has a propagation delay of 15ns.

Q,+Q,* X = 0 X = 1 Q,Q2 X = 0 X = 1 00 01 10 01 10 00 10 00 01 1

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