(a) If logic blocks of Figure 6-1(a) are used, how many LUTs are required to build a 4-bit adder with accumulator?

(b) If an FPGA with built-in carry-chain logic as shown in Figure 6-11 is used, how many 4-input LUTs are required?

(c) Design a 4-bit adder-subtracter with accumulator using an FPGA with carry-chain logic and 4-input LUTs. Assume a control signal Su which is 0 for addition and 1 for subtraction. Show the required connections on a diagram similar to that shown in Figure 6-11 and give the function realized by each LUT.

Figure 6-1(a)

Figure 6-11

Transcribed Image Text:

Carry-in Programmable LUT FF bi Dedicated Carry Chain | Logic Block Il Carry Programmable LUT FF bz - Dedicated Carry Chain _Logic Block 21 Carry Programmable LUT FF Dedicated Carry Chain Logic Block nl Carry Programmable LUT FF Carry-out Dedicated Carry Chain Logic Block n+1l Figure 6-11: Carry Chains for Fast Addition Based on Xilinx.