(a) Write a Verilog module for a LUT with four inputs and three outputs. The 3-bit output should be a binary number equal to the number of 1s in the LUT input.
(b) Write a Verilog module for a circuit that counts the number of 1s in a 12-bit number. Use three of the modules from (a) along with overloaded addition operators.
(c) Simulate your code and test it for the following data inputs:

111111111111, 010110101101, 100001011100