An 8-bit right-shift register with parallel load is to be implemented using an FPGA with logic blocks as shown in Figure 6-1(a). The flip-flops are labeled X₇X₆X₅X₄X₃X₂X₁X₀. The control signals N and S operate as follows: N = 0, do nothing; NS = 11, right shift; NS = 10, load. The serial input for right shift is SI. 

(a) How many logic blocks are required?
(b) Show the required connections for the rightmost block on a copy of Figure 6-1(a). Connect N to CE.
(c) Give the function generator outputs for this block.

X1 | X2 X Function FF CE generator X3 LUT4 X4 Y1 Y Function QY D. FF CE generator Y3 LUT4 Y4 Figure 6-1: Example Bailding Blocks for an FPGA (a) With Look up Tables and flip-flops