Construct an SM chart that is equivalent to the following state table. Test only one variable in
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Output (Z,Z,Z,) 11 Next State X,X, = 00 01 S, S, S, S, S, S, S, So Present State 10 11 X,X2 = 00 01 10 100 110 010 001 001 So 001 001
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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