In the following Verilog code, A, B, C, and D are 0 at time 10 ns. If D changes to 1 at 20 ns, specify the times at which A, B, and C will change and the values they will take.

(a)  always @(D)
begin
#5 A <= 1;
B <= A + 1;
#10 C <= B;
end

(b) always @(D)
begin
A <= #5 1;
B <= A + 1;
C <= #10 B;
end