Digital Design Using VHDL A Systems Approach 1st Edition William J. Dally, R. Curtis Harting, Tor M. Aamodt - Solutions

Find the dual function of the following function and write it in normal form: f(x,y,z) = (x ^y) V (χ ^2) V ( ^z).
Prove that the absorption property is true by using perfect induction (i.e., enumerate all the possibilities).
Prove that the associative property is true.
Prove that the distributive property does not work for distributing + over × with integers.
Write down the logic function that describes the conditions under which the switch network of Figure 4.27(b) connects its two terminals.Data in Figure 4.27(b) - f T [X] e a a' C
Draw a schematic using NFETs and PFETs for a restoring logic gate that implements the function f= ((a A b) Ve) v (d ^e).
Draw a series–parallel switch circuit that implements the function f(w, x, y, z) = 1 if at least one input is true.
Draw a series–parallel switch circuit that implements the function f(x, y, z) = 1 if inputs xyz represent either 1 or a prime number in binary (xyz = 001, 010, 011, 101, 111).
Write down the logic function implemented by the CMOS circuit of Figure 4.28(c). Data in Figure 4.28(c). T ²dC sa d edh sb SC scol NFETS (c) X
For both 130 nm and 28 nm technologies, calculate the resistance and gate capacitance of a PFET with W = 40Lmin. What are the width and gate capacitance of an NFET with twice the resistance of the W = 40Lmin PFET? Assume all transistors have L = Lmin.
Write down the logic function implemented by the CMOS circuit of Figure 4.28(a). Data in Figure 4.28(a) 의 의 bd 으이ㄷ 40 (a) X
Write down the logic function implemented by the CMOS circuit of Figure 4.28(b). Data in Figure 4.28(b). T PFETS 의[ 의ㄷ (b) X
Draw the transistor implementation for a three-input NAND gate.
Draw the transistor implementation for a four-input NOR gate.
Draw a schematic using NFETs and PFETs for a restoring logic gate that implements the function f = 0 if and only if cba = 010, 011, 101, or 111. Assume that all inputs and their complements are available.
Draw a schematic using NFETs and PFETs for a restoring logic gate that implements the function ∫ = 0 if zero or two of inputs cba are true. Assume that all inputs and their complements are available.

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