Question: For the flip-flops in the counter in Figure 5.24, assume that t su = 3 ns, t h = 1 ns, and the propagation delay

For the flip-flops in the counter in Figure 5.24, assume that t_su = 3 ns, t_h = 1 ns, and the propagation delay through a flip-flop is 1 ns. Assume that each AND gate, XOR gate, and 2-to-1 multiplexer has the propagation delay equal to 1 ns. What is the maximum clock frequency for which the circuit will operate correctly?

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