A CPU produces the following sequence of read addresses in hexadecimal: 54, 58, 104, 5C, 108, 60,

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A CPU produces the following sequence of read addresses in hexadecimal:
54, 58, 104, 5C, 108, 60, F0, 64, 54, 58, 10C, 5C, 110, 60, F0, 64.
Supposing that the cache is empty to begin with, and assuming an LRU replacement, determine whether each address produces a hit or a miss for each of the following caches:

(a) direct mapped in Figure 12-3.

(b) fully associative in Figure 12-4.

(c) two-way set associative in Figure 12-6.

Figure 12-3

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Figure 12-4

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Figure 12-6

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Logic And Computer Design Fundamentals

ISBN: 9780133760637

5th Edition

Authors: M. Morris Mano, Charles Kime, Tom Martin

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