A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for

Question:

A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for the multiple- cycle computer. The instruction stores the contents of eight registers in eight consecutive memory locations. Register R[SA] specifies the address in memory M to which the first register R[SB] is to be stored. The registers to be stored are R[SB], R[(SB+1)
modulo 8], . . ., R[(SB+7)modulo 8] in Memory M addresses R[SA], R[SA] +1, . . ., R[SA]+7. Design this instruction presenting your final results in the form shown in Table 8-15.

Table 8-15.