A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for

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A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for the multiple- cycle computer. The instruction stores the contents of eight registers in eight consecutive memory locations. Register R[SA] specifies the address in memory M to which the first register R[SB] is to be stored. The registers to be stored are R[SB], R[(SB+1)
modulo 8], . . ., R[(SB+7)modulo 8] in Memory M addresses R[SA], R[SA] +1, . . ., R[SA]+7. Design this instruction presenting your final results in the form shown in Table 8-15.

Table 8-15.

State Table for Illustration of Instructions Having Three or More Cycles Inputs State Next State I L PS DX

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Related Book For  answer-question

Logic And Computer Design Fundamentals

ISBN: 9780133760637

5th Edition

Authors: M. Morris Mano, Charles Kime, Tom Martin

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