## Question:

A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for the multiple- cycle computer. The instruction stores the contents of eight registers in eight consecutive memory locations. Register R[SA] specifies the address in memory M to which the first register R[SB] is to be stored. The registers to be stored are R[SB], R[(SB+1)

modulo 8], . . ., R[(SB+7)modulo 8] in Memory M addresses R[SA], R[SA] +1, . . ., R[SA]+7. Design this instruction presenting your final results in the form shown in Table 8-15.

**Table 8-15.**

**Transcribed Image Text:**

## State Table for Illustration of Instructions Having Three or More Cycles Inputs State Next State I L PS DX Outputs Opcode VCNZ EXO 0010001 XXXX EX1 0 00 1000 0XXX XXXX X 0000 1 1 X EX1 0010001 XXXX INF 0 01 0XXX 1000 XXXX X 0000 1 1 AX M BX MB FS MD RW MM W 0 0 EXO 0001101 XXXO EX1 0 00 1000 0XXX XXXX X 0000 EXO 0001101 XXXI INF 0 01 1000 0XXX XXXX X 0000 EX1 0001101 XXXO EX2 0 00 1001 XXXX XXXX 1 1100 EX1 0001101 XXX1 INF 0 01 1001 XXXX XXXX 1 1100 EX2 0001101 XXXX EX3 0 00 1000 XXXX 1000 0 1101 0 EX3 0001101 XXX0 EX2 0 00 1001 1001 XXXX X 0110- 0 EX3 0001101 XXXI EX4 0 00 1001 1001 XXXX X 0110 0 1 EX4 0001101 XXXX INF 0 01 0XXX 1000 XXXX X 0000 0 1 EXO 0001110 XXXO EX1 0 00 1000 0XXX XXXX X 0000 0 EXO 0001110 XXX1 INF 0 01 1000 0XXX XXXX X 0000 0 EX1 0001110 XXXO EX2 0 00 1001 XXXX XXXX 1 1100 0 EX1 0001110 XXX1 INF 0 01 1001 XXXX XXXX 1 1100 0 EX2 0001110 XXXX EX3 0 00 1000 XXXX 1000 0 1110 0 EX3 0001110 XXX0 EX2 0 00 1001 1001 XXXX X 0110 0 EX3 0001110 XXX1 EX4 0 00 1001 1001 XXXX X 0110 0 EX4 0001110 XXXX INF 0 01 0XXX 1000 XXXX X 0000 0 *For this state and input combination, PC-PC+1 also occurs. 000 0 LRI X 0 LRI 1 X 0 SRM R8 -R[SA], Z: EXI 1 X 0 SRM R8 R[SA], Z: INF* 1 X 0 SRM R9zf OP, Z:-EX2 1 1 1 1 X 0 SRM X 0 SRM 1 1 X 0 SRM 1 1 1 1 1 xxx X X X X X X X X 0 SRM 0 SRM 0 SLM 0 SLM 0 SLM 0 SLM 0 SLM 0 SLM Comments X 0 SLM X 0 SLM R8- - M[R[SA]]. - EX1 R[DR] M[R8], INF* R9-zf OP, Z: INF* R8sr R8,- EX3 R9 R9 -1, Z: -EX2 R9 R9-1, Z: EX4 R[DR] - R8, -> INF* R8- -R[SA], Z: - EX1 R8 R[SA], Z:INF* R9-zf OP, Z: EX2 R9zf OP, Z: INF* R8sl R8. EX3 R9-1, Z: EX2 R9-1, Z: EX4 R9 R9 R[DR] -R8. IF*