A serial odd parity generator is to be designed. A binary sequence of arbitrary length is presented to the parity generator on input X. When a given bit is presented on input X, the corresponding odd parity bit for the binary sequence is to appear during the same clock cycle on output Z. To indicate that a sequence is complete and that the circuit is to be initialized to receive another sequence, input Y becomes 1 for one clock cycle. Otherwise, Y is 0.

(a) Find the state diagram for the serial odd parity generator.

(b) Find the state table for the serial odd parity generator.

(c) Write an HDL description for the state machine for the odd parity generator using VHDL or Verilog as a template.