Compile and simulate the 2-to-4-line decoder Verilog description in Figure 20 for sequence 000, 001, 010, 011, 100, 101, 110, 111 on E, A0, A1. Verify that the circuit functions as a decoder.

Data From Figure 20

A0 12-to-4-Line decoder 4 2-input ANDs 8 2-input ANDs 64 2-input ANDs D D Do A D 3-to-8-Line decoder A2 A4 Do 4 2-input ANDS 8 2-input ANDs D 12-to-4-Line decoder 3-to-8-Line decoder As D D D6 63 6-to-64-Line decoder