Consider the following sequence of instructions

In all instructions, the destination operand is given last. Initially, registers RO and R2 contain 2000 and 50, respectively. These instructions are executed in a computer that has a four-stage pipeline similar to that shown in Figure 8.2. Assume that the first instruction is fetched in clock cycle 1, and that instruction fetch requires only one clock cycle.

(a) Draw a diagram similar to Figure 8.2a. Describe the operation being performed by each pipeline stage during each of clock cycles 1 through 4.

(b) Give the contents of the interstage buffers, B1, B2, and B3, during clock cycles 2 to 5.

Add #20,R0,R1 Mul #3,R2, R3 And # $3A,R2, R4 Add RO,R2,R5