1. [10] Given an MIPS instruction: Label: beq $s0, $s1, Label. Assume the processor is the...

  

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1. [10] Given an MIPS instruction: Label: beq $s0, $s1, Label. Assume the processor is the same as the one shown in Figure 4.24 in the textbook. a) What is the value of control bit "ALUSrc"? What operation is the ALU configured to perform? b) What value is the output of "Shift left2" module? PC Instruction [25-0] Add Read address Instruction [31-0] Instruction memory 26 Shift left 2, Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-11] Instruction [15-0] Jump address [31-0] 28 Control PC +4 [31-28] RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read register 2 16 Read data 1 Write Read register data 2 Write data Registers Sign- extend 32 Instruction [5-0] Shift left 2 M u ALU Add result Zero ALU ALU result ALU control Address MUX Read data Write Data data memory MIX) FIGURE 4.24 The simple control and datapath are extended to handle the jump instruction. An additional multiplexor (at the upper right) is used to choose between the jump target and either the branch target or the sequential instruction following this one. This multiplexor is controlled by the jump control signal. The jump target address is obtained by shifting the lower 26 bits of the jump instruction left 2 bits, effectively adding 00 as the low-order bits, and then concatenating the upper 4 bits of PC + 4 as the high-order bits, thus yielding a 32-bit address. 1. [10] Given an MIPS instruction: Label: beq $s0, $s1, Label. Assume the processor is the same as the one shown in Figure 4.24 in the textbook. a) What is the value of control bit "ALUSrc"? What operation is the ALU configured to perform? b) What value is the output of "Shift left2" module? PC Instruction [25-0] Add Read address Instruction [31-0] Instruction memory 26 Shift left 2, Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-11] Instruction [15-0] Jump address [31-0] 28 Control PC +4 [31-28] RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read register 2 16 Read data 1 Write Read register data 2 Write data Registers Sign- extend 32 Instruction [5-0] Shift left 2 M u ALU Add result Zero ALU ALU result ALU control Address MUX Read data Write Data data memory MIX) FIGURE 4.24 The simple control and datapath are extended to handle the jump instruction. An additional multiplexor (at the upper right) is used to choose between the jump target and either the branch target or the sequential instruction following this one. This multiplexor is controlled by the jump control signal. The jump target address is obtained by shifting the lower 26 bits of the jump instruction left 2 bits, effectively adding 00 as the low-order bits, and then concatenating the upper 4 bits of PC + 4 as the high-order bits, thus yielding a 32-bit address.

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