$1.(20$ points$)$ The following sequence of instruction is executed in a basic fivestage pipelined processor discussed in the class. There is NO forwarding support.

$```$

ldur x$2,[$x$1,$#$0]$

add x$3,$x$3,$x$2$

add x$4,$x$1,$x$3$

sub x$1,$x$4,$x$1$

cbz x$1,$ exit

stur x$3,[$x$1,$#$0]$

ldur x$5,[$x$1,$#$8]$

sub x$2,$x$5,$x$6$

add x$6,$x$2,$x$3$

exit:

add x$1,$x$2,$x$3$

$```$

$($a$)$ List all hazards in the above code. For each hazard, indicate the instruction which creates the hazard and all affected instructions.

$($b$)$ Rewrite the code including minimum number of nop instructions to eliminate potential hazards. You can reorder the instructions. Assume that the pipeline has full forwarding support. Also, assume that register read and write at the same address can happen in one clock cycle.

$($c$)$ Could branch prediction help eliminate the hazards in the code for this question? Please explain why or why not in one or two sentences.