$12\mathrm{.}1\mathrm{.}3$ Give the total delay of the $4-$bit ripple carry adder shown in Fig. $12\mathrm{.}3$ if all gates have a delay of $2$ ns $.$

Fig. $12\mathrm{.}3$

$4-$bit RCA timing exercise $12\mathrm{.}1\mathrm{.}4$ Give the total delay of the $4-$bit ripple carry adder shown in Fig. $12\mathrm{.}3$ if the XOR gates have delays of $10$ ns $,$ while the AND and OR gates have delays of $2$ ns $.$