Uses Xilinx Vivado suite

1. Write VHDL/ Verilog code for half adder circuit shown below using a) Gate-level modeling (instantiating EX-OR and AND gates) b) Dataflow modeling c) Behavioral modeling Write a test bench to verify functionality. 2. Write VHDL/ Verilog code for Full Adder circuit shown below using a) Gate-level modeling (by instantiating Half adder design in part A) b) Behavioral modeling. Write a test bench to verify functionality. 3. Write VHDL/ Verilog code for 4 Bit Ripple Carry Adder circuit shown below by instantiating Full Adder design in part B. Write a test bench to verify functionality