Question: 1 & 2 please! 1. Determine the circuit first and then write the dataflow verilog version (Only the Assign Statements) of the following HDL code-

1 & 2 please!

1. Determine the circuit first and then write the dataflow verilog version (Only the Assign Statements) of the following HDL code- module comb_ckt_1(x,f); input [0:3] x; output f; wire nl, n2, n3, n4, n5, n6; not go(nl, x[0]), gl(n4, n3); and g2(n2, x[1], nl), g3(n3, x[1], x[2]), g4n5, x[2], x[3])); g5(n6, x[1], n4),); or g6(f, n2, n5, n6), endmodule 2. Consider an 8-bit input. Determine if the 8-bits contain even number 1s

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