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Q1: Given the following Combinational circuit, Use Verilog HDL on Quartus tool to Io I 12 Iz 4 to 1 MUX Si So 2 to 1 MUX Output S2 14 Is 16 I 4 to 1 MUX Si So 1. Write a Verilog HDL code to describe the module mux4x1 // this module name must be your last name 2. Write a Verilog HDL code to describe the module mux2x1// this module name must be your first name 3. Write a Verilog HDL code to describe the whole system structurally from its subsystems // this module name must be your university number Q2: Problem: Design and Simulation of 8-bit ALU Design an 8-bit ALU circuit that receives two 8-bit input numbers X 17:0) and Y17:01, and produces a 8-bit output 2 [7:0), an output carry Cout, an overflow flag ov, and Zero flag. The circuit implements the following 12 functions based on a 3-bit control input [3:0): Code 000 001 010 011 100 101 110 111 Function Addition: 2X+Y Subtraction: 2-X-Y Reminder: 2X Y Bitwise AND: 2-X&Y Bitwise OR: 2 X Y Concatenate: 2X13:0), 7(3:0) Equality: Zero-X-Y Less than: Cout-X