1 Cinescale Ing / Ips 3 module ALU + Iparameter SIZE - 4) (A, D, Select, Out); 4 Input (SIZE-1101 2. B: 5 5 6 output reg SIZE-110) Out: 7 // select-- 1 SUM) // let. - 2 SURTRACT) 9 10 Dalways g begin 11 F if Select == 1) begin 12 Out - A + B : 13 end 14 ala bagin 15 Out -- B end 17 end 10 endnodule 19 sh ST 30666 LOS S cime scale in / lps 2 2 module testbench 1); parameter SIZE - 5 4 5 5 7 reg SIZE-110 A, 9 10 11 12 13 14 13 16 17 10 19 // Booth FSM variables reg start, CLK, EST: wire EST , CLK_OUT: wire (1:0) alate; wire (3:0) Outsoater // dacapath variables wira (2 SIZE-1:0) Output; 21 23 27 wire [6:0) seq_u,9_outi, seg_out2, sec_003 reg 19:01 9e_inl, 9e4_in2,249_ins; Bootha_75 +1.SIZE (SIZE) Boocha_SH 1.acars (atart), care state),.CEE (CLK), NST (OSTI...ST_OUF (DS3_000)..CK_000CLK_OUT]..at_State (Out_Stacell: datapath 11.SIZE (SIZE) datapath (101),.in2(B), state(atate),CLK (CLK_ot), .ST (65_out),,Output (Outputy]: Segrens7 cmentl (.bcd Oac_state). -309 (904_0CC)); // 7 cment to check out atate Galways begin // J parts 7 segments will change depending on SIZE variable 7 E if (S12E) begin acc_Ini - 1104-SIZE) [1'60},Output[SIZE:01: seg 102 - 0 aeg_33 - 0 ent else 12 SIZE = begin seq_inl - Output 15:01 aeg_an2-11-SIZE)|1'60, Output[SIZE-:[]); _ - 0 end else if (SIZE (1a egin aeg_inl - Output 310) SC_3n2 - Outp:41 sec_1n3- [[(12-SIZE) [1'60, Output[SIZE-1:4]]: 29 30 31 32 33 34 35 37 end 40 41 acc_inl - Outper 13:01: seq_3n2 - Output 17:41 seg in Output111]: 45 end end 47 43 49 50 51 52 53 54 segrent segent (bad seg_inl), .ages_outl!! // segment to first + bits of catgut agent7 accent 3 (.bcd (209_in2), .300 (209_out211; // 7 acent to accond 4 bits of our Segrens7 segmentu (.bcd.g_in), ..eg (seg_out}: 11 7 segment to third 4 bits of outpat 56 57 50 59 60 61 alwaya CLK-CEE: lancial began GLK OF RST - #10: RST - 1107 63 start - 1001 A-+; 65 4100 67 B-5: Piniat: end 1 72 73 74 75 endtrodule QUESTION JUST EXPLAIN THE VERILOG CODES STEP BY STEP