1. Consider a 4-processor multiprocessor connected with a shared bus that has the following properties centralized shared memory accessible with the bus, (ii) snooping- based MSI cache coherence protocol, (iii write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. The processors issue the following five requests, one after the other. Create a table similar to that in slide 4 of lecture 25 to indicate what happens for every request. (50 points) Pl Write X o P2: Read X o P3: Write X o P2: Write X o P4: Read X 1. Consider a 4-processor multiprocessor connected with a shared bus that has the following properties centralized shared memory accessible with the bus, (ii) snooping- based MSI cache coherence protocol, (iii write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. The processors issue the following five requests, one after the other. Create a table similar to that in slide 4 of lecture 25 to indicate what happens for every request. (50 points) Pl Write X o P2: Read X o P3: Write X o P2: Write X o P4: Read X