1. Consider a 4-processor multiprocessor connected with a shared bus that has the following properties: (i) centralized shared memory accessible with the bus, (ii) snooping-based MSI cache coherence protocol, (iii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. The processors issue the following five requests, one after the other. Create a table similar to that in slide 4 of lecture 25 to indicate what happens for every request. (50 points)

P1: Write X

P2: Read X

P3: Write X

P2: Write X

P4: Read X

2. Consider a 4-processor multiprocessor connected with a scalable network that has the following properties: (i) distributed memory organization, (ii) directory-based cache coherence protocol, (iii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. Assume that data X is stored in the memory connected to processor P2. Create a table similar to that in slide 11 of lecture 25 to indicate what happens for every request. (50 points)

P1: Write X

P2: Read X

P3: Write X

P2: Write X

P4: Read X