Consider a 3-processor multiprocessor connected with a shared bus that has the following properties: () centralized shared memory accessible with the bus, (ii) snooping-based MSI cache coherence protocol, (ii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. The processors issue the following five requests, one after the other. Create a table similar to that in slide 6 of lecture 25 to indicate what happens for every request. (35 points) 2. o o o o o P1: Read X P1: Write X P3: Read X P2: Read X P3: Write X Request Cache Re Request on Who State in State inState in State in Hit/Miss the bus responds Cache 1 Cache 2 Cache 3 Cache4