1) Design a clocked synchronous state machine, using D F/F, that counts the number of ones on the input signal, A. The output, Z, is asserted whenever the number of ones on clock-ticks since the machine's start-up is divisible by 5 Thus 0, 5, 10, 15, 20 ones would all give an output of Z=1. (Another way of describing this is that the number of ones is=0(mod5).) Use the simplest assignment strategy where the state value (Q2Q1Q0) corresponds to the remainder when divided by five (0, 1, 2, 3 & 4). Also show any unused states and account for their next state and output as don't-care values. (75 Marks) You must show state diagram (20 marks) with state assignment, state transition table (20 marks), k-map minimisation (20 marks) and logic circuit with D F/F (15 marks). All D F/Fs are clock positive edge triggered. 1) Design a clocked synchronous state machine, using D F/F, that counts the number of ones on the input signal, A. The output, Z, is asserted whenever the number of ones on clock-ticks since the machine's start-up is divisible by 5 Thus 0, 5, 10, 15, 20 ones would all give an output of Z=1. (Another way of describing this is that the number of ones is=0(mod5).) Use the simplest assignment strategy where the state value (Q2Q1Q0) corresponds to the remainder when divided by five (0, 1, 2, 3 & 4). Also show any unused states and account for their next state and output as don't-care values. (75 Marks) You must show state diagram (20 marks) with state assignment, state transition table (20 marks), k-map minimisation (20 marks) and logic circuit with D F/F (15 marks). All D F/Fs are clock positive edge triggered