Question: 1 . For a direct - mapped cache design with a 6 4 - bit address, the following bits of the address are used to

1. For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-10
9-5
4-0
a. What is the cache block size (in words)?
Offset bits =5, words =2^4=32 words
b. How many blocks does the cache have?
c. What is the ratio between total bits required for such a cache implementation over the data storage bits?

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