$1)$ How many simultaneous and how many concurrent instruction streams can we support in each of the four schemes? $2)$ What is the size $($in bits$)$ of the registers in the execution contexts of each chip? $3)$ Which one of chips b$,$ c$,$ d offers the maximum memory latency reduction and which the minimum? $4)$ How many pieces of independent work are needed to run each chip with max latency hiding ability? Which chip between c and d offers the max latency hiding ability? Why? $5)$ For which chip do you believe that the compiler does the heaviest work? Why? $6)$ For which chip do you believe that the compiler does the lightest work? Why? $7)$ Under which circumstances $($nature and characteristics of programs run on each$)$ does the chip b$)$ have better performance than chip d$)$ and vice$-$versa? $8)$ Assume that you know you are running a program that has high temporal locality. What do you think is preferable in this case? $1)$ To have a large cache and no or few hardware threads, $2)$ To have a small or no cache but many hardware threads, $3)$ to have large cache and many hardware threads.