1. LOAD R, #1 // R <- 1 2. LOAD S, #1 // S <- 1 3. LOAD T, #(k-2) // T <- k-2 4. ADD AC, R, S // AC <- R+S 5. T-- // T <- T-1 6. LOAD R, S // R <- S 7. LOAD S, AC // S <- AC 8. BRP 4, T 9. STOR M, AC // M <- AC where R, S, T, AC are registers, M is a memory location, # denotes numeric value and BRP X, Y stands for \branch to X if Y is positive".

Show the pipeline activity when the code is executed on a pipelined computer with input value k=4. There are ve pipeline stages: fetch, decode, register read, execute and write back, and there is an instruction cache on board (initially empty) that can store ten decoded instructions. You can assume that certain instructions skip some of the stages, but make these assumptions explicit.