1. Referencing to the DATA PATH TEMPLATE. If the instruction (Reg[Rd] = Reg[Rs] + Reg[Rt]) is the only instruction to be supported by the processor, ADD Rd, Rs, Rt (a) what is the clock cycle time (in ps)? (5 points) Answer: Use the latency of each block below. l-memory = 250 ps registers 90 ps ALUmux = 20 ps Regmux 20 ps ALU Data-memory = 250 ps - 100 ps (b) What is the clock rate in G Hz (giga Hertz) in (a)? (5 points) (c) If LW (Load Word) is the only instruction to be supported by the processor, what is the clock cycle time (in ps)? (5 points) Answer: is the clock cycle time (in ps) and clock rate in GHz (5 points)? (d) If the processor needs to support both ADD and LW instruction, what Answer: 2. (7 points) Reference to the DATA PATH TEMPLATE. The instruction ADD Rd, Rs, Rt does Reg [Rd] Reg [Rs] + Reg [Rt] Fill in the values of the control signals generated for this instruction. RegWrite = Mem Read = Memwrite = ALUperation = ALUmux = Regmux = Branch = Note: the meaning of each control signal is given below