Problem 1:

Consider the following instruction:

AND Rd, Rs, Rt

Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt]

What are the values of the control signals generated by this control function?

RegDst		ALUOp
Branch		MemWrite
MemRead		ALUSrc
MemtoReg		RegWrite

Which resources/blocks perform useful function for this instruction?

Which resources/blocks produce outputs, but their outputs are not used for this instruction? Which produce no outputs?

Problem 2:

The basic single-cycle MIPS implementation in the provided figure can only implement some instructions. New instructions can be added to an existing instruction set architecture (ISA), but the decision whether or not to do that depends, among other things, on the const and complexity the proposed addition introduces into the processor datapath and control. For this problem, refer to the following proposed new instruction:

LWI Rt,Rd(Rs)

Interpretation: Reg[Rt] = Mem[Reg[Rd] + Reg[Rs]]

Which existing blocks, if any, can be reused for this instruction?

Which new functional blocks (if any) are needed for this instruction?

What new signals do we need (if any) from the control unit to support this instruction?