[10] Consider a 64-byte direct mapped cache with 8 byte blocks. Virtual addresses are 16 bits. Each page is 128 bytes. The cache is physically tagged. The processor has 1 KB of physical memory. Assume pages 0-4 of the physical memory have been occupied. a) 2) How large would a single-level page table be, given that each page requires 4 protection bits, and entries must be an integral number of bytes. b) Assume the cache is initialized empty, the CPU needs to access memory with the following virtual address sequence: 0048, 0108, 200s, 2048, 2088, 0048, 0108, and 2008. For each memory access, decide whether it is a page hit or page fault, and whether it is a cache hit or cache miSS