[11] A processor has a 32 bytes main memory and an 8 bytes 4-way set associative cache. Table 0 . shows the current state of the cache. Write hit or miss (H or M) under each address in the memory reference. Show the new state of the cache for each miss in a new table, label the table with address, and circle the change. Assume that "00110" and "11011" were the last two addresses to be accessed. Use the Least Recently Used (LRU) replacement policy. Table 0 . Initial State of the cache Table 1. After handling address "10011," Hit / Miss ( ) Table 2. After handling address " 000012" Hit / Miss ( ) Table 3. After handling address " 001102" Hit / Miss ( ) Table 4. After handling address " 010102" Hit / Miss ( ) Table 5. After handling address "01110," Hit / Miss ( )