Question: A processor has a 128 byte memory( 7-bit address) and 32 byte, 4-way set associative cache, block size is 4 bytes. Table Q shows the

A processor has a 128 byte memory( 7-bit address) and 32 byte, 4-way set associative cache, block size is 4 bytes. Table Q shows the current state of the cache. Use the Least Recently Used replacement policy, the number before tag represents the block history, most recently used is 3. Write hit or miss under the each address in the memory reference sequence below. Show the new state of the cache for each miss in a new table, label the table with the address, and circle the change

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