12 Consider an 8-bit bit-parallel ALU with only four functions: add, subtract, and bitwised AND and XOR. Assume an adder/subtractor module uses a hybrid adder designed from CLA(2) modules. In addition, the overflow flag must be masked out when performing bitwise computation. Assume only 8-bit, 2-to-1 MUXs are available. Do the following: a. Draw the data path and estimate its propagation delay assuming 0.1ns delay for each NOT and NAND gate. b. Construct the truth table for its Map module. 12 Consider an 8-bit bit-parallel ALU with only four functions: add, subtract, and bitwised AND and XOR. Assume an adder/subtractor module uses a hybrid adder designed from CLA(2) modules. In addition, the overflow flag must be masked out when performing bitwise computation. Assume only 8-bit, 2-to-1 MUXs are available. Do the following: a. Draw the data path and estimate its propagation delay assuming 0.1ns delay for each NOT and NAND gate. b. Construct the truth table for its Map module