16 5.2 Design a 128M x 16 memory using RAM chips that are 32M x 8. Draw the chips and main components and connections. Indicate all inputs/ outputs: R/W, CS, data in, data out, decoder and chip's address lines. [6] 5.3 How many address bits are required to access all addresses of 128M X memory? [2] 5.4 How many of these lines are connected to the address inputs of all chips? [2] 5.5 How many of adress lines must be decoded for the chip select inputs? [2] 5.6 Specify the size of the decoder. [2] 5.7 How many data in/out bits constitute the data bus? [2] 5.8 How many chips of 32M X 8 are required to provide a memory of 128M x 16? [2] 5.9 Is this design of wider or longer memory? [2] 5.10 What are the capacity and width of 128M x 16 memory? [2]