1.(a) Using the example:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY ckt1 IS

PORT (a, b, c : IN STD_LOGIC;

f, g : OUT STD_LOGIC);

END ckt1;

ARCHITECTURE LogicFunc OF ckt1 IS

BEGIN

f <= ((NOT a) AND b AND c) OR (a AND (NOT b) AND (NOT c)) OR (a AND b AND c);

g <= ((NOT a) OR (NOT b)) AND (a OR C);

END LogicFunc;

write VHDL code to implement the following functions.

f = ac0 + bc0 + c 0 d 0 + ab + ad0 g = (a + c 0 )(a + b + d 0 )(b + c 0 + d 0 )

(b) Use CAD tool based functional simulation to check if f = g. Demonstrate CAD simulation to TA for checkoff.