Rewrite the VHDL code for the sum_of_minterms entity making use of only CSA statements (no port maps).

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity sum_of_minterms is port ( a, b, c,: in STD_LOGIC; output : out STD_LOGIC ); end sum_of_minterms;

architecture asum_of_minterms of sum_of_minterms is begin output

Introduction Consider the following truth table defning a three vaiable Boolean function: Table 1: Some arbitrary Boolean Function. OUT The function may be expressed in sum-of-minterms form as: OUT = ABC + AB C + A B C . The gate level hardware implementation of the function is shown in Figure 1 OUT Figure 1: Two-level sum of minterms hardware implementation