1.a) Write a Verilog module that implements a 1-bit half adder.

b) Through instantiating the module in a) plus other logic, implement a 1-bit full adder with Verilog.

c) Finally, design and implement a 4-bit binary full adder with Verilog.

d) Write a proper test-bench and stimulus, thoroughly test your 4 -bit binary adder.

e) Show a waveform snapshot that indicates you adder can correctly compute 0101 + 1101 and show your results.

2.a) Write a Verilog module that implements a 1-bit partial full adder (PFA).

b) Through instantiating the module in a) plus other logic, implement a 4-bit full adder with Verilog.

c) Write a proper test-bench and stimulus, thoroughly test your 4 bit carry lookahead adder.

d) Show a waveform snapshot that indicates you adder can correctly compute 0101 + 1101 and show your results.

3. a) Assuming that each gate, no matter which type, will have 1 time unit delay. From the logic design diagram, estimate the worst case totol delay of these 2 types of 4-bit adders. Find out the delay ratio between these two adders.

b) Using Vivado, simulate both designs and use 0101+1101 as the example, show the reported delays. Find out the delay ratio between these two adders.

c) Are the ratios in a) and b) the same?