Building and testing basic combinational circuits using Verilog HDL

Description: Build and test the following circuits using gate-level modeling in Verilog HDL.

1. 3-input majority function.

2. Conditional inverter (see the table below: x - control input, y - data input). Do NOT use XOR gates for the implementation.

x	y	Output
0		y
1		y'

3. Two-input multiplexer (see the table below: x,y - data inputs, z - control input).

z	Output
0	x
1	y

4. 1-bit half adder.

5. 1-bit full adder by cascading two half adders.

6. 1-bit full adder directly (as in fig. 4.7 in the text).

7. 4-bit adder/subtractor with overflow detection by cascading four 1-bit full adders (see fig. 4.13 in the text).

Requirements:

1. Create truth tables and use maps for simplification (not needed for circuits 5 and 7).
2. Create a module for each circuit, instantiate it in a test module and test it.
3. The hierarchical circuits (5 and 7) should use instances of their constituent modules.
4. For testing use all combinations of input values and show the corresponding output for all circuits except for the 4-bit adder/subtractor.
5. For the 4-bit adder/subtractor include all combinations of positive, negative and 0 inputs, as well as all overflow situations and show the inputs/outputs both in binary and signed decimal.

Extra: Implement an ABCD-to-seven-segment decoder with the modification that the six invalid combinations of the input should be used as don't care conditions. Reuse components if possible to minimize the circuit. Test the circuit with all decimal digits. Include in the report the maps for all functions, the gate level diagrams, and the Verilog code and test results.