Question: 2 0 p t s Problems in this question refer to a clock cycle in which the processor fetches the following instruction: sw $ r

20pts Problems in this question refer to a clock cycle in which the processor fetches the following instruction:
sw $r0,20($r1)
Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which the above instruction word is fetched:
\table[[10,r,12,r,14,rs,r8,rB,12,31],[0,-1,2,-3,-4,10,6,8,2,-16]]
(Let the content of PC be 010000000)
I. [4pts+4pts] What are the outputs of the sign-extend and the jump "Shift left 2" unit (near the top of Figure 1) for this instruction word?
II.[4 pts] For each Mux (Four Mux in Figure 1), show the values of its data output during the execution of this instruction. (If the output of the MUX does not matter for the instruction, you can write the output as 'don't care')
III. [4pts] What are the values of these registers after the execution of this instruction
\table[[r0,r1,r2,r3,r4,r5,r6,r8,r12,r31],[,,,,,,,,,]]
IV.[4pts] What is the new PC address after this instruction is executed?
2 0 p t s Problems in this question refer to a

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