$2.(20$ pts$)$ A block diagram of the single$-$cycle MIPS processor and the latencies of the logic blocks are given below.

$\backslash$begin$\{$tabular$\}\{|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|\}$

$\backslash$hline $\backslash$begin$\{$tabular$\}\{$c$\}$

I$-$Mem$/$D$-\backslash \backslash$

Mem

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Register $\backslash \backslash$

File

$\backslash$end$\{$tabular$\}$ & Mux & ALU & Adder & Single Gate & $\backslash$begin$\{$tabular$\}\{$c$\}$

Register $\backslash \backslash$

Read

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Register $\backslash \backslash$

Setup

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Sign $\backslash \backslash$

Extend

$\backslash$end$\{$tabular$\}$ & Control $\backslash \backslash$

$\backslash$hline $250$ ps & $150$ ps & $25$ ps & $200$ ps & $150$ ps & $5$ ps & $30$ ps & $20$ ps & $50$ ps & $50$ ps $\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$

a$.(8$ pts$)$ Highlight$/$draw the execution path $($starting from PC$)$ in the figure above for an Rformat instruction. Do not forget to show the path that updates PC$.$

b$.(12$ pts$)$ Given the values in the table, calculate the exection time for ADD R$1,$ R$2,$ R$3.$ Show your work $($write a formula, not just numbers$).$ Do not worry about the controller.

Execution Time: